View OP467GS-REEL_8971392.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

pin connections 14-lead ceramic dip (y suffix) and 14-lead plastic dip (p suffix) 1 2 3 4 5 6 7 14 13 12 11 10 9 8 out a ?n a +in a v+ +in b ?n b out b out d ?n d +in d v +in c ?n c out c + + ++ op467 rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a quad precision, high-speed operational amplifier op467 features high slew rate C 170 v/ s wide bandwidth C 28 mhz fast settling time C <200 ns to 0.01% low offset voltage C <500 v unity-gain stable low voltage operation 5 v to 15 v low supply current C <10 ma drives capacitive loads applications high-speed image display drivers high frequency active filters fast instrumentation amplifiers high-speed detectors integrators photo diode preamps general description the op467 is a quad, high-speed, precision operational ampli- fier. it offers the performance of a high-speed op amp combined with the advantages of a precision operational amplifier all in a single package. the op467 is an ideal choice for applications where, traditionally, more than one op amp was used to achieve this level of speed and precision. the op467? internal compensation ensures stable unity-gain operation, and it can drive large capacitive loads without oscilla- tion. with a gain bandwidth product of 28 mhz driving a 30 pf load, output slew rate in excess of 170 v/ s, and settling time to 0.01% in less than 200 ns, the op467 provides excellent dynamic accuracy in high-speed data-acquisition systems. the channel-to-channel separation is typically 60 db at 10 mhz. the dc performance of op467 includes less than 0.5 mv of offset, voltage noise density below 6 nv/ hz and total supply current under 10 ma. common-mode rejection and power supply rejection ratios are typically 85 db. psrr is maintained to better than 40 db with input frequencies as high as 1 mhz. the low offset and drift plus high speed and low noise, make the op467 usable in applications such as high-speed detectors and instrumentation. the op467 is specified for operation from 5 v to 15 v over the extended industrial temperature range (?0 c to +85 c) and is available in 14-lead plastic and ceramic dip, plus 16-lead soic and 20-terminal lcc surface mount packages. contact your local sales office for mil-std-883 data sheet and availability. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: www.analog.com fax: 781/326-8703 ? analog devices, inc., 2001 16-lead soic (s suffix) 1 2 3 4 5 6 7 8 out a in a +in a v+ +in b in b out b 16 15 14 13 12 11 10 9 out d in d +in d v +in c in c out c nc nc op467 nc = no connect +in in out v+ v figure 1. simplified schematic 20-terminal lcc (rc suffix) +in d v +in c nc nc 4 5 6 7 9 19 20 1 2 3 18 17 16 15 14 8 10 11 12 13 (top view) +in a v+ +in b nc nc out a in a out d in d nc in b out b in c out c nc op467 nc = no connect
op467?pecifications electrical characteristics parameter symbol conditions min typ max unit input characteristics offset voltage v os 0.2 0.5 mv ?0 c t a +85 c1mv input bias current i b v cm = 0 v 150 600 na v cm = 0 v, 40 c t a +85 c 150 700 na input offset current i os v cm = 0 v 10 100 na v cm = 0 v, 40 c t a +85 c 10 150 na common-mode rejection cmr v cm = 12 v 80 90 db cmr v cm = 12 v, 40 c t a +85 c8088 db large signal voltage gain a vo r l = 2 k ? 83 86 db r l = 2 k ? , ?0 c t a +85 c77.5 db offset voltage drift ? v os / ? t 3.5 v/ c bias current drift ? i b / ? t 0.2 pa/ c long term offset voltage drift ? v os / ? t note 1 750 v output characteristics output voltage swing v o r l = 2 k ? 13.0 13.5 v r l = 2 k ? , ?0 c t a +85 c 12.9 13.12 v power supply 2 power supply rejection ratio psrr 4.5 v v s = 18 v 96 120 db ?0 c t a +85 c 86 115 db supply current i sy v o = 0 v 8 10 ma v o = 0 v, ?0 c t a +85 c13ma supply voltage range v s 4.5 18 v dynamic performance gain bandwidth product gbp a v = +1, c l = 30 pf 28 mhz slew rate sr v in = 10 v step, r l = 2 k ? , c l = 30 pf a v = +1 125 170 v/ s a v = ? 350 v/ s full-power bandwidth bw v in = 10 v step 2.7 mhz settling time t s to 0.01%, v in = 10 v step 200 ns phase margin 0 45 degrees input capacitance common mode 2.0 pf differential 1.0 pf noise performance voltage noise e n p-p f = 0.1 hz to 10 hz 0.15 v p-p voltage noise density e n f = 1 khz 6 nv/ hz current noise density i n f = 1 khz 8 pa/ hz notes 1 long-term offset voltage drift is guaranteed by 1000 hrs. life test performed on three independent wafer lots at 125 c, with an ltpd of 1.3. 2 for proper operation the positive supply must be sequenced on before the negative supply. specifications subject to change without notice. rev. d C2C (@ v s = 15.0 v, t a = 25 c unless otherwise noted.)
electrical characteristics parameter symbol conditions min typ max unit input characteristics offset voltage v os 0.3 0.5 mv ?0 c t a +85 c1mv input bias current i b v cm = 0 v 125 600 na v cm = 0 v, ?0 c t a +85 c 150 700 na input offset current i os v cm = 0 v 20 100 na v cm = 0 v, ?0 c t a +85 c 150 na common-mode rejection cmr v cm = 2.0 v 76 85 db cmr v cm = 2.0 v, ?0 c t a +85 c76 80 db large signal voltage gain a vo r l = 2 k ? 80 83 db r l = 2 k ? , ?0 c t a +85 c74 db offset voltage drift ? v os / ? t3 5 v/ c bias current drift ? i b / ? t 0.2 pa/ c output characteristics output voltage swing v o r l = 2 k ? 3.0 3.5 v r l = 2 k ? , ?0 c t a +85 c 3.0 3.20 v power supply power supply rejection ratio psrr 4.5 v v s = 5.5 v 92 107 db ?0 c t a +85 c 83 105 db supply current i sy v o = 0 v 8 10 ma v o = 0 v, ?0 c t a +85 c12ma dynamic performance gain bandwidth product gbp a v = +1 22 mhz slew rate sr v in = 5 v step, r l = 2 k ? , c l = 39 pf a v = +1 90 v/ s a v = ? 90 v/ s full-power bandwidth bw v in = 5 v step 2.5 mhz settling time t s to 0.01%, v in = 5 v step 280 ns phase margin 0 45 degrees noise performance voltage noise e n p-p f = 0.1 hz to 10 hz 0.15 v p-p voltage noise density e n f = 1 khz 7 nv/ hz current noise density i n f = 1 khz 8 pa/ hz specifications subject to change without notice. (@ v s = 5.0 v, t a = 25 c unless otherwise noted.) op467 rev. d C3C
op467 rev. d C4C wafer test limits 1 parameter symbol conditions limit unit offset voltage v os 0.5 mv max input bias current i b v cm = 0 v 600 na max input offset current i os v cm = 0 v 100 na max input voltage range 2 12 v min/max common-mode rejection ratio cmrr v cm = 12 v 80 db min power supply rejection ratio psrr v = 4.5 v to 18 v 96 db min large signal voltage gain a vo r l = 2 k ? 83 db min output voltage range v o r l = 2 k ? 13.0 v min supply current i sy v o = 0 v, r l = 10 ma max notes 1 electrical tests and wafer probe to the limits shown. due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and test ing. 2 guaranteed by cmr test. absolute maximum ratings 1 supply voltage 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v input voltage 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v differential input voltage 3 . . . . . . . . . . . . . . . . . . . . . . 26 v output short-circuit duration . . . . . . . . . . . . . . . . . . limited storage temperature range y, rc packages . . . . . . . . . . . . . . . . . . . . ?5 c to +175 c p, s packages . . . . . . . . . . . . . . . . . . . . . . ?5 c to +150 c operating temperature range op467a . . . . . . . . . . . . . . . . . . . . . . . . . . ?5 c to +125 c op467g . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0 c to +85 c junction temperature range y, rc packages . . . . . . . . . . . . . . . . . . . . ?5 c to +175 c p, s packages . . . . . . . . . . . . . . . . . . . . . . ?5 c to +150 c lead temperature range (soldering, 60 sec) . . . . . . . . 300 c package type a 4 jc unit 14-lead cerdip (y) 94 10 c/w 14-lead plastic dip (p) 76 33 c/w 16-lead soic (s) 88 23 c/w 20-terminal lcc (rc) 78 33 c/w notes 1 absolute maximum ratings apply to both dice and packaged parts, unless otherwise noted. 2 for proper operation the positive supply must be sequenced on before the negative supply. 3 for supply voltages less than 18 v, the absolute maximum input voltage is equal to the supply voltage. 4 ja is specified for the worst-case conditions, i.e., ja is specified for device in socket for cerdip, p-dip, and lcc packages; ja is specified for device soldered in circuit board for soic package. ordering guide temperature package package model ranges descriptions options op467arc/883c ?5 c to +125 c 20-terminal lcc e-20a op467ay/883c ?5 c to +125 c 14-lead cerdip q-14 op467gbc die op467gp ?0 c to +85 c 14-lead plastic dip n-14 op467gs ?0 c to +85 c 16-lead soic r-16 OP467GS-REEL ?0 c to +85 c 16-lead soic r-16 dice characteristics op467 die size 0.111 0.100 inch, 11,100 sq. mils sub- strate is connected to v+, number of transistors 165 (@ v s = 15.0 v, t a = 25 c unless otherwise noted.)
op467 rev. d C5C 80 30 20 1k 10k 100m 10m 1m 100k 40 50 60 70 10 0 10 20 0 90 180 phase shift degrees open-loop gain db frequency hz gain phase v s = 15v r l = 1m c l = 30pf tpc 1. open-loop gain, phase vs. frequency 80 40 20 100k 100m 10m 1m 10k 20 0 60 frequency hz closed-loop gain db v s = 15v t a = 25 c tpc 2. closed-loop gain vs. frequency 25 0 20 15 5 5 10 0 20 15 10 supply voltage volts open-loop gain v/mv t a = +125 c t a = +25 c t a = 55 c tpc 3. open-loop gain vs. supply voltage typical performance characteristics 100 60 0 1k 100k 10k 100 40 20 80 frequency hz impedance v s = 15v t a = 25 c 1m a vcl = +100 a vcl = +10 a vcl = +1 tpc 4. closed-loop output impedance vs. frequency 0.0 100k 1m 10m 0.1 0.2 0.3 0.1 0.2 0.3 gain error db frequency hz 3.4 5.8 v s = 5v v s = 15v tpc 5. gain linearity vs. frequency 30 15 0 10k 10m 1m 100k 1k 10 5 20 25 frequency hz maximum output swing volts a vcl = 1 a vcl = +1 v s = 15v t a = 25 c r l = 2k tpc 6. max v out swing vs. frequency
op467 rev. d C6C 12 6 0 10k 10m 1m 100k 1k 4 2 8 10 frequency hz maximum output swing volts v s = 5v t a = 25 c r l = 2k a vcl = 1 a vcl = +1 tpc 7. max v out swing vs. frequency 120 60 0 10k 10m 1m 100k 1k 40 20 80 100 frequency hz common-mode rejection volts v s = 15v t a = 25 c tpc 8. common-mode rejection vs. frequency 120 60 0 1k 1m 100k 10k 100 40 20 80 100 frequency hz power supply rejection db v s = 15v t a = 25 c tpc 9. power-supply rejection vs. frequency 60 0 1600 30 10 200 20 0 50 40 1400 1000 800 600 1200 400 load capacitance pf overshoot % v s = 15v r l = 2k v in = 100mv p-p a vcl = +1 a vcl = 1 tpc 10. small signal overshoot vs. load capacitance 60 0 1600 30 10 200 20 0 50 40 1400 1000 800 600 1200 400 load capacitance pf overshoot % v s = 5v r l = 2k v in = 100mv p-p a vcl = +1 a vcl = 1 2)0"" ##(
4 0 60 10 40 10k 100m 10m 1m 100k 20 30 40 50 30 20 10 0 gain db frequency hz v s = 15v 10000pf 1000pf 500pf 200pf c in = network analyzer tpc 12. noninverting gain vs. capacitive loads
op467 rev. d C7C 0 50 100 1k 100m 10m 1m 100k 10k 40 30 20 10 90 80 70 60 frequency hz channel separation db v s = 15v 100 tpc 13. channel separation vs. frequency 12 6 0 100 11k 10 4 2 8 10 frequency hz input current noise density pa/ hz 5v v s 15v tpc 14. input current noise density vs. frequency 100 10 1.0 0.1 1 10k 1k 100 10 frequency hz nv/ hz tpc 15. voltage noise density vs. frequency 500 2 0 0 1 1 2 400 300 200 100 time ns v out error mv v s = 15v v in = 5v c l = 50pf 3 4 3 4 tpc 16. settling time, negative edge 500 2 0 0 1 1 2 400 300 200 100 time ns v out error mv v s = 15v v in = 5v c l = 50pf 3 4 3 4 tpc 17. settling time, positive edge 20 20 5 0 0 5 5 10 15 15 10 20 10 15 supply voltage volts input voltage range volts t a = 25 c tpc 18. input voltage range vs. supply voltage
op467 rev. d C8C 0 100k 100m 10m 1m 10k 10 20 10 gain db frequency hz v s1 = 15v v s2 = 5v r l = 10k c l = 50pf v s1 = 15v v s2 = 5v 20 30 40 50 30 40 50 tpc 19. noninverting gain vs. supply voltage 14 4 0 10 2 6 8 12 output swing volts 100 10k 1k 10 load resistance positive swing negative swing v s = 15v t a = 25 c tpc 20. output swing vs. load resistance 2 0 5 1 3 4 output swing volts 100 10k 1k 10 load resistance positive swing negative swing v s = 5v t a = 25 c tpc 21. output swing vs. load resistance 500 0 400 300 100 50 200 100 400 350 300 250 200 150 100 50 0 input offset voltage v os v units v s = 15v t a = 25 c 1252 op amps tpc 22. input offset voltage distribution 500 0 400 300 100 50 200 100 400 350 300 250 200 150 100 50 0 input offset voltage v os v units v s = 5v t a = 25 c 1252 op amps tpc 23. input offset voltage distribution tc v os v/ c 500 0 5.0 300 100 0.5 200 0 400 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 units v s = 15v t a = 25 c 1252 op amps tpc 24. tc v os distribution
op467 rev. d C9C tc v os v/ c 500 0 5.0 300 100 0.5 200 0 400 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 units v s = 5v t a = 25 c 1252 op amps tpc 25. tc v os distribution 60 40 75 125 55 45 50 50 75 100 50 25 0 25 29.0 27.0 28.5 27.5 28.0 temperature c phase margin degrees gain bandwidth product mhz gbw m v s = 15v r l = 2k tpc 26. phase margin and gain bandwidth vs. temperature 400 0 125 100 50 50 75 200 150 250 300 350 100 75 50 25 0 25 temperature c slew rate v/ s +sr sr v s = 5v r l = 2k a vcl = 1 tpc 27. slew rate vs. temperature 400 0 125 100 50 50 75 200 150 250 300 350 100 75 50 25 0 25 temperature c slew rate v/ s sr +sr v s = 5v r l = 2k a vcl = +1 tpc 28. slew rate vs. temperature 650 250 125 350 300 50 75 450 400 500 550 600 100 75 50 25 0 25 temperature c slew rate v/ s v s = 15v r l = 2k a vcl = 1 +sr sr tpc 29. slew rate vs. temperature 400 0 125 100 50 50 75 200 150 250 300 350 100 75 50 25 0 25 temperature c slew rate v/ s v s = 15v r l = 2k a vcl = +1 +sr sr tpc 30. slew rate vs. temperature
op467 rev. d C10C 10 10 400 4 8 100 6 0 2 2 0 4 6 8 300 200 5 1 4 2 3 1 5 0 2 3 4 settling time ns output step for 15v supply volts output step for 5v supply volts 0.1% 0.01% 0.1% 0.01% r f = 5k t a = 25 c tpc 31. settling time vs. output step 10 0 20 6 2 5 4 0 8 15 10 supply voltage volts supply current ma t a = +125 c t a = +25 c t a = 55 c tpc 32. supply current vs. supply voltage 200 0 125 120 40 50 80 75 160 100 75 50 25 0 25 temperature c input bias current na v s = 15v tpc 33. input bias current vs. temperature 25 0 125 15 5 50 10 75 20 100 75 50 25 0 25 temperature c input offset current na v s = 15v tpc 34. input offset current vs. temperature
op467 rev. d C11C applications information output short-circuit performance to achieve a wide bandwidth and high slew rate, the op467 output is not short circuit protected. shorting the output to ground or to the supplies may destroy the device. for safe operation, the output load current should be limited so that the junction temperature does not exceed the absolute maximum junction temperature. to calculate the maximum internal power dissipation, the fol- lowing formula can be used: p tt d a a = j j max where t j and t a are junction and ambient temperatures respec- tively, p d is device internal power dissipation, and j a is pack- aged device thermal resistance given in the data sheet. unused amplifiers it is recommended that any unused amplifiers in a quad package be connected as a unity gain follower with a 1 k ? feedback resistor with noninverting input tied to the ground plain. printed circuit board layout considerations satisfactory perfo rmance of a high-speed op amp largely de pends on a good pc layout. to achieve the best dynamic performance, following high frequency layout technique is recommended. grounding a good ground plain is essential to achieve the optimum perfor- mance in high-speed applications. it can significantly reduce the undesirable effects of ground loops and ir drops by providing a low impedance reference point. best results are obtained with a multilayer board design with one layer assigned to ground plain. to maintain a continuous and low impedance ground, avoid running any traces on this layer. power supply considerations for proper operation the positive supply must be sequenced on before the negative supply. all users should take steps to ensure this. in high frequency circuits, device lead length introduces an inductance in series with the circuit. this inductance, combined with stray capacitance, forms a high frequency resonance circuit. poles generated by these circuits will cause gain peaking and additional phase shift, reducing the op amp s phase margin and leading to an unstable operation. a practical solution to this problem is to reduce the resonance frequency low enough to take advantage of the amplifier s power supply rejection. this is easily done by placing capacitors across the supply line and the ground plain as close as possible to the device pin. since capacitors also have internal parasitic components, such as stray inductance, selecting the right capacitor is important. to be effective, they should have low impedance over the frequency range of interest. tantalum capacitors are an excellent choice for their high capacitance/size ratio, but their esr (effective series resistance) increases with frequency making them less effective. on the other hand, ceramic chip capacitors have excel- lent esr and esl (effective series inductance) performance at higher frequencies, and because of their small size, they can be placed very close to the device pin, further reducing the stray inductance. best results are achieved by using a combination of these two capacitors. a 5 f 10 f tantalum parallel with a 0.1 f ceramic chip caps are recommended. if additional isola- tion from high frequency resonances of the power supply is needed, a ferrite bead should be placed in series with the supply lines between the bypass caps and the power supply. a word of caution, addition of the ferrite bead will introduce a new pole and zero to frequency response of the circuit and could cause unstable operation if it is not selected properly. +v s 10 f tantalum 0.1 f ceramic chip v s 10 f tantalum 0.1 f ceramic chip + figure 2. recommended power supply bypass signal considerations input and output traces need special attention to assure a mini- mum stray capacitance. input nodes are very sensitive to capaci- tive reactance, particularly when connected to a high impedance circuit. stray capacitance can inject undesirable signals from a noisy line into a high impedance input. protect high impedance input traces by providing guard traces around them. this will also improve the channel separation significantly. additionally, any stray capacitance in parallel with the op amp s input capacitance generates a pole in the frequency response of the circuit. the additional phase shift caused by this pole will reduce the circuit s gain margin. if this pole is within the gain range of the op amp, it will cause unstable performance. to reduce these undesirable effects, use the lowest impedance where pos- sible. lowering the impedance at this node places the poles at a higher frequency, far above the gain range of the amplifier. stray capacitance on the pc board can be reduced by making the traces narrow and as short as possible. further reduction can be realized by choosing smaller pad size, increasing the spacing between the traces, and using pc board material with a low dielectric constant insulator (dielectric constant of some com- mon insulators: air = 1, teflon = 2.2, and fr4 = 4.7; with air being an ideal insulator). removing segments of the ground plain directly under the input and output pads is recommended. outputs of high-speed amplifiers are very sensitive to capacitive loads. a capacitive load will introduce a pair of pole and zero to the circuit s frequency response, reducing the phase margin, leading to unstable operation or oscillation. teflon is a registered trademark of e.i. du pont co.
op467 rev. d C12C generally, it is a good design practice to isolate the amplifier s output from any capacitive load by placing a resistor between the amplifier s output and the rest of the circuits. a series resis- tor of 10 ? to 100 ? is normally sufficient to isolate the output from a capacitive load. the op467 is internally compensated to provide stable opera- tion, and is capable of driving large capacitive loads without oscillation. sockets are not recommended since they increase the lead inductance/capacitance and reduce the power dissipation of the package by increasing the leads thermal resistance. if sockets must be used, use teflon or pin sockets with the shortest possible leads. phase reversal the op467 is immune to phase reversal; its inputs can exceed the supply rails by a diode drop without any phase reversal. output input 10 0% 100 90 200 s 10v 10v v1 15.8v figure 3. no phase reversal (a v = +1) saturation recovery time the op467 has a fast and symmetrical recovery time from either rail. this feature is very useful in applications such as high-speed instrumentation and measurement circuits, where the amplifier is frequently exposed to large signals that overload the amplifier. 10 0% 100 90 5v dly 9.842 s 20ns 5v figure 4. saturation recovery time, positive rail 10 0% 100 90 5v dly 4.806 s 20ns 5v figure 5. saturation recovery time, negative rail high-speed instrumentation amplifier the op467 performance lends itself to a variety of high-speed applicati ons, including high-speed precision instrumen tation amplifiers. figure 6 represents a circuit commonly used for data acqui sition, ccd imaging, and other high-speed applica tions. circuit gain is set by r g . a 2 k ? resistor will set the circuit gain to 2; for unity gain, remove r g . for any other gain settings use the following formula: g = 2/r g resistor value is in k ? r c is used for adjusting the dc common-mode rejection, and c c is used for ac common-mode rejection adjustments. output v in +v in 1k 2k 1k 2k 10k 10k 5pf 1.9k 2k c c r g r c 200 10t figure 6. a high-speed instrumentation amplifier 2.5mv 2.5mv 0.01% 10v step v s = 15v neg slope figure 7. instrumentation amplifier settling time to 0.01% for a 10 v step input (negative slope)
op467 rev. d C13C 2.5mv 2.5mv 0.01% 10v step v s = 15v pos slope figure 8. instrumentation amplifier settling time to 0.01% for a 10 v step input (positive slope) error to scope to input to in-amp output 2k 2k ad9617 549 1k 61.9 +v s v s + + figure 9. settling time measurement circuit 2 mhz biquad bandpass filter the circuit in figure 10 is commonly used in medical imaging ultrasound r eceivers. the 30 mhz bandw idth is sufficient to accurately produce the 2 mhz center frequency, as the measured response shows in figure 11. when the op amp s bandwidth is too close to the filter s center frequency, the amplifier s internal phase shift causes excess phase shift at 2 mhz, which alters the filter s response. in fact, if the chosen op amp has a bandwidth close to 2 mhz, the combined phase shift of the three op amps will cause the loop to oscillate. careful consideration must be given to the layout of this circuit as with any other high-speed circuit. if the phase shift introduced by the layout is large enough, it could alter the circuit performance, or worse, it will oscillate. 2k r1 3k v in r3 2k r2 2k r4 2k r5 2k c2 50pf c1 50pf r6 1k v out + + + + 1/4 op467 1/4 op467 1/4 op467 1/4 op467 figure 10. 2 mhz biquad filter 20 100k 100m 10m 1m 10k 10 0 40 30 frequency hz gain db figure 11. biquad filter response
op467 rev. d C14C 15 v dd v ref a r fb a i out 1a i out 2a/ i out 2b i out 1b r fb b v ref b dgnd r fb c i out 1c i out 2c/ i out 2d v ref c i out 1d r fb d v ref d dac8408 +5v +10v +10v v out a v out b 0.1 f +15v 15v c2 10pf c1 10pf 0.1 f 7 op467 5 4 11 6 op467 2 3 1 1 2 3 7 8 9 10 11 12 4 5 6 13 14 + +10v +10v v out a v out b digital control signals c3 10pf c4 10pf 14 12 13 op467 db0 (lsb) db1 db2 db3 db4 db5 8 10 9 op467 (msb) db7 db6 28 27 26 22 21 20 19 18 17 25 24 23 16 + + + r/ w a/ b ds1 ds2 figure 12. quad dac unipolar operation fast i-to-v converter the fast slew rate and fast settling time of the op467 are well suited to the fast buffers and i-to-v converters used in variety of applications. the circuit in figure 12 is a unipolar quad d/a converter consisting of only two ics. the current output of the dac8408 is converted to a voltage by the op467 configured as an i-to-v converter. this circuit is capable of settling to 0.1% within 200 ns. figures 13 and 14 show the full-scale settling time of the outputs. to obtain reliable circuit performance, keep the traces from the dac s i out to the inverting inputs of the op467 short to minimize parasitic capacitance. 10 0% 100 90 260.0ns 2v 50mv 100ns figure 13. voltage output settling time 10 0% 100 90 251.0ns 2v 50mv 100ns figure 14. voltage output settling time r fb i out 3pf op467 i-v dac-8408 1k 50 604 60.4 2k dc offset 2k ad847 figure 15. dac v out settling time circuit
op467 rev. d C15C op467 spice macro-model * node assignments noninverting input inverting input positive supply negative supply output * . subckt op467 1 2 99 50 27 * * input stage * i1 4 50 10e 3 cin 1 2 1e 12 ios 1 2 5e 9 q1 528 qn q2 679 qn r3 99 5 185 . 681 r4 99 6 185 . 681 r5 8 4 180 . 508 r6 9 4 180 . 508 eos 7 1 poly (1) (14,20) 50e 61 eref 98 0 (20,0) 1 * * gain stage and dominant pole at 1.5 khz * r7 10 98 3 . 714e6 c2 10 98 28 . 571e 12 g1 98 10 (5,6) 5 . 386e 3 v1 99 11 1 . 6 v2 12 50 1 . 6 d1 10 11 dx d2 12 10 dx rc 10 28 1 . 4e3 cc 28 27 12e 12 * * common-mode stage with zero at 1.26 khz * ecm 13 98 poly (2) (1,20) (2,20) 0 0 . 5 0 . 5 r8 13 14 1e6 r9 14 98 25 . 119 c3 13 14 126 . 721e 12 * * pole at 400e6 * r10 15 98 1e6 c4 15 98 0 . 398e 15 g2 98 15 (10,20) 1e 6 * * output stage * isy 99 50 8 . 183e 3 rmp1 99 20 96 . 429e3 rmp2 20 50 96 . 429e3 ro1 99 26 200 ro2 26 50 200 l1 26 27 1e 7 go1 26 99 (99,15) 5e 3 go2 50 26 (15,50) 5e 3 g4 23 50 (15,26) 5e 3 g5 24 50 (26,15) 5e 3 v3 21 26 50 v4 26 22 50 d3 15 21 dx d4 22 15 dx d5 99 23 dx d6 99 24 dx d7 50 23 dy d8 50 24 dy * * models used * . model qn npn (bf=33.333e3) . model dx d . model dy d (bv=50) . ends op467 g2 r10 c4 98 e ref i sy rmp2 rmp1 20 15 g4 d7 d5 d3 d4 g5 d8 d6 23 24 22 21 v3 v4 g01 r02 r01 g02 l1 99 50 26 15 99 50 27 + + + figure 16. spice macro-model output stage i os c in i1 e os r3 5 g1 99 50 99 50 n n+ 2 1 r4 6 r5 r6 4 7 c2 r7 10 98 12 v2 e ref r c 28 c3 r8 e cm 14 c c 27 v1 11 13 d2 d1 r9 + + + + + q1 q2 89 figure 17. spice macro-model input and gain stage
op467 rev. d C16C outline dimensions dimensions shown in inches and (mm). c00302cC0C4/01(d) printed in u.s.a. 14-lead plastic dip (p suffix) (n-14) 14 17 8 pin 1 0.795 (20.19) 0.725 (18.42) 0.280 (7.11) 0.240 (6.10) 0.100 (2.54) bsc seating plane 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.022 (0.558) 0.014 (0.356) 0.160 (4.06) 0.115 (2.93) 0.070 (1.77) 0.045 (1.15) 0.130 (3.30) min 0.195 (4.95) 0.115 (2.93) 0.015 (0.381) 0.008 (0.204) 0.325 (8.25) 0.300 (7.62) 16-lead soic (s suffix) (r-16) seating plane 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.050 (1.27) bsc 16 9 8 1 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40) pin 1 0.4133 (10.50) 0.3977 (10.00) 0.0125 (0.32) 0.0091 (0.23) 8 0 0.0291 (0.74) 0.0098 (0.25) 45 0.0500 (1.27) 0.0157 (0.40) 14-lead cerdip (y suffix) (q-14) 14 17 8 0.310 (7.87) 0.220 (5.59) pin 1 0.005 (0.13) min 0.098 (2.49) max 0.100 (2.54) bsc 15 0 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) seating plane 0.200 (5.08) max 0.785 (19.94) max 0.150 (3.81) min 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) 20-terminal leadless ceramic chip carrier (rc suffix) (e-20a) 1 20 4 9 8 13 19 14 3 18 bottom view 0.028 (0.71) 0.022 (0.56) 45 typ 0.015 (0.38) min 0.055 (1.40) 0.045 (1.14) 0.050 (1.27) bsc 0.075 (1.91) ref 0.011 (0.28) 0.007 (0.18) r typ 0.095 (2.41) 0.075 (1.90) 0.100 (2.54) bsc 0.200 (5.08) bsc 0.150 (3.81) bsc 0.075 (1.91) ref 0.358 (9.09) 0.342 (8.69) sq 0.358 (9.09) max sq 0.100 (2.54) 0.064 (1.63) 0.088 (2.24) 0.054 (1.37) op467?evision history location page data sheet changed from rev. c to rev. d. footnote added to power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 footnote added to max ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 edits to power supply considerations section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

▲Up To Search▲

Price & Availability of OP467GS-REEL

	To Download OP467GS-REEL Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .